SSD1306 is a single-chip CMOS OLED/PLED driver and controller for organic/polymer light-emitting diode dot matrix graphic display systems. It consists of 128 segments and 64 commons. This integrated circuit is designed for ordinary cathode type OLED panels.
SSD1306 embeds contrast control, display RAM and oscillator, reducing the number of external components and power consumption of the display. It has 256 steps of brightness control. Data/commands are sent through the hardware-optional general-purpose MCU 6800/8000 series compatible parallel interface, I2C interface or serial peripheral interface. It is suitable for many compact portable applications, such as mobile phone sub-displays, MP3 players, calculators, etc.
(1) Cathode OLED. This is because the chip limits the polarity of the OLED.
(2) 128 segments and 64 public areas -----> horizontal 128 points and vertical 64 points
Selection of MCU interface
The interface of SSD1306 MCU is composed of 8 data pins and 5 control pins. The pin assignment modes of different interfaces are shown in Table 8-1. Different MCU modes can be set by hardware selection on the BS[2:0] pins (see Table 7-1 for BS[2:0] settings).
The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#
The 6800 bidirectional data interface has 8 data lines,
One R/W# (read and write control line [low level means writing, high level means reading]),
One D/C# (data/command selection line [low level represents commands, high level represents data]),
E (total enable line),
CS# (chip select [active low]).
(1) R/W# line, low level signal means writing data to the chip, high level means reading data from the chip.
(2) D/C# line, the low level indicates the read or write of the command, and the high level indicates the read or write of the data.
The meaning of the icon:
(1) During the falling edge of the E pin: CS# low level indicates that the chip is selected (the selected chip is a prerequisite for reading and writing):
R/W# low level-----D/C# low level means: write command
R/W# low level-----D/C# high level means: write data
R/W# high level-----D/C# low level means: read command
R/W# high level-----D/C# high level means: read data
The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#.
8 bidirectional data ports,
RD# (read enable [active low]),
WR# (write enable [active low]),
D/C# (data/command selection [high level data, low level command])
CS# (chip select [active low]).
Timing interpretation: when cs# remains low, the rising edge of wr# input is used as a data/command write latch signal
Write command: CS# is low level, D/C# is low level, WR# is low level, RD# is high level.
The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode
SCLK: clock line
SDIN: data line
D/C#: data or command line (low level command line, high level data line)
CS#: Chip select line (active low)
Chip selection is selected—>Command or data is set—>Set the rising edge of the clock (SCLK is pulled low for a period of time and then pulled high) during which the data is put on the data line.
3-wire SPI: SCLK, SDIN, CS# these three lines, but there is no D/C# line. Only write operations are allowed. The timing operation is the same as 4-wire.
IIC interface: IIC timing
Introduction to OLED:
OLED distribution map:
There are 128 horizontal dots, 64 vertical dots, and 64 vertical dots are divided into 8 pages, each with 8 dots.
SSD1306 has 3 different memory addressing modes: page addressing mode, horizontal addressing mode and vertical addressing mode. This command sets the memory addressing method to one of the above methods
In the page addressing mode, after reading/writing the display RAM, the column address pointer increments and automatically increments by 1. If the column address pointer reaches the column end address, the column address pointer is reset to the column start address and the page address pointer does not change. The user must set a new page and column address in order to access the next page of RAM content page and move the column address point of the sequential page addressing mode as shown in Figure 10-1
In the normal display data RAM read or write and page addressing mode, the following steps are required to define the start RAM access pointer position:
• Set the page start address of the target display position to B0h-B7h through commands.
• Set the lower starting column address of the pointer by commands 00h~0Fh.
• Set the upper starting column address of the pointer by commands 10h~1Fh.
For example, if the page address is set to B2h, the lower column address is 03h, and the upper column address is 00h,
This means that the starting column is SEG3 of PAGE2. The location of the RAM access pointer is shown in the figure:
void OLED_Set_Pos(unsigned char x, unsigned char y)
OLED_WR_Byte(0xb0+y,OLED_CMD); //Set the page address b0-b7 to indicate pages 1-8
OLED_WR_Byte((((x)&0xf0)>>4)|0x10,OLED_CMD); //Set the upper starting column address of the pointer by command 10h~1Fh
OLED_WR_Byte(((x)&0x0f),OLED_CMD); //Set the lower starting column address of the pointer by command 00h~0Fh
Horizontal addressing mode (A[1:0]=00b)
In the horizontal addressing mode, after reading/writing the display RAM, the column address pointer increases automatically by 1. If the column address pointer reaches the column end address, the column address pointer is reset to the column start address, and the page address pointer is increased by 1. The page and column address points of the horizontal addressing mode are shown in Figure 10-3. When the page address pointer reaches the end address, the pointer is reset to the column start address and the page start address.
Vertical addressing mode: (A[1:0]=01b)
In the vertical addressing mode, after reading/writing the display RAM, the page address pointer increases automatically by 1. If the page address pointer reaches the page end address, the page address pointer will be reset by the page start address and the column address pointer will increase by one. The sequence of page movement column address points in the vertical addressing mode are shown in Figure 10-4. When the column and page address pointers reach the end address at the same time, the pointers are reset to the column start address and page start address.
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